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PIC Assembly Instruction Set | Midrange Devices

Each midrange instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The
midrange Instruction Set Summary in the table below lists the instructions recognized by the MPASM assembler. The instruction set is highly orthogonal and is grouped into three basic categories:

  • Byte-oriented operations
  • Bit-oriented operations
  • Literal and control operations

For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the
instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction.

For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located.

For literal and control operations, 'k' represents an eight or eleven bit constant or literal value.

All instructions are executed in one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In these cases, the execution takes two instruction cycles with the second cycle executed as an NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 ms. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 ms.

The following instructions are applicable to midrange devices (PIC12 and PIC16)

Mnemonic,
Operands
Description Cycles 14-Bit Instruction Word Status
Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF    f,d
ANDWF     f,d
CLRF    f
CLRW     -
COMF     f,d
DECF     f,d
DECFSZ     f,d
INCF     f,d
INCFSZ     f,d
IORWF     f,d
MOVF     f,d
MOVWF     f,d
NOP      -
RLF      f,d
RRF     f,d
SUBWF     f,d
SWAPF     f,d
XORWF    f,d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff
00 0101 dfff ffff
00 0001 1fff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 1fff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
00 0010 dfff ffff
00 1110 dfff ffff
00 0110 dfff ffff
C,DC,Z
Z
Z
Z
Z
ZZ

Z
Z

C
C
C,DC,Z

Z

BIT-ORIENTED FILE REGISTER OPERATIONS
BCF     f,b
BSF     f,b
BTFSC     f,b
BTFSS     f,b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
LITERAL AND CONTROL OPERATIONS
ADDLW     k
ANDLW     k
CALL     k
CLRWDT     -
GOTO     k
IORLW     k
MOVLW     k
RETFIE     -
RETLW     k
RETURN     -
SLEEP     -
SUBLW     k
XORLW     k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
11 110x kkkk kkkk
11 1010 kkkk kkkk
C,DC,Z
ZTO,PD

Z

TO,PD
C,DC,Z
Z

Instruction Opcode Format

PIC assembly opcode format

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