Delays to PCB production almost never first arise during the factory processing stage. Hidden risks that slow down progress are already planted weeks earlier in CAD files, in small details that no one stopped to examine closely.
A typical process often unfolds like this: Your circuit design passes simulation tests, the internal review meeting concludes smoothly with no issues, your team packages the Gerber files intended for production and sends them to your partner PCB factory. Then the factory's CAM engineer opens the compressed package, spots an ambiguous detail at a glance that makes direct production impossible, and immediately sends an engineering inquiry. The entire production process grinds to a halt; the factory can only resume work after someone on your team provides a clear response. One inquiry may delay production by a day. If the engineer in charge of coordination happens to be travelling on business, three consecutive clarifications can drag the process out by a full week. What could have been completed in 5 days quietly stretches into three weeks.
What is most frustrating is that these problems are almost never complex, rare difficulties. They are all recurring small oversights, and every time production is delayed, the same five issues come up over and over again.
The first is the design of annular rings and spacing, which defaults to the assumption that all layers of the circuit board can align perfectly.
The layout software you use to draw designs will allow you, without any obstruction, to place a 0.3mm pad over a drilled hole with a diameter of 0.25mm. On a computer screen, this design looks correct in all the test layouts you have tried. But in the factory's production workshop, actual manufacturing conditions are completely different from the ideal state in the computer: when the circuit board's multiple layers are laminated, slight misalignments occur between layers; the drill bit used to bore holes may also deviate slightly, so the copper traces you drew in the design file cannot perfectly match the actual position of the drilled hole.
If the remaining width of the annular ring is lower than the minimum value the factory can stably guarantee, you will only face two outcomes: either the factory sends an inquiry asking if you accept scenarios where the annular ring touches the edge of the drilled hole, or even a section of the copper ring is missing, and production cannot resume until you make a decision; or the factory cannot follow standard production processes and can only quietly lower the yield rate, which ultimately still translates to a delivery delay for you.
These proven rules of thumb are worth adding to your DRC to avoid these pitfalls starting from the design phase:
For standard processes, the inner-layer annular ring must be at least 0.15mm (6 mils) wide. The outer layer can be slightly narrower, but not by too much.
The minimum distance from a drilled hole to an adjacent copper trace must be maintained at 0.2mm, to prevent a deviated drill bit from cutting into neighbouring traces.
Pad dimensions must be calculated starting from the final finished hole size, not the drilled hole size: finished hole size + plating thickness + twice the annular ring width + layer alignment error.
There is a more critical reminder here: all your design rules must be set against the production capacity parameters published by your partner factory, and you must not directly use the default settings that come with your CAD software. Those default parameters are written for general scenarios and cannot meet the requirements of production-ready PCB manufacturing.
2. Leaving Stack-Up Design Entirely to the Factory
Leaving stack-up design entirely for the factory to arrange leads to more redesigns in high-speed circuit board design than most other mistakes.
Many designers fall into this pit in a strikingly similar way: they open an impedance calculator, plug in generic parameters for standard FR-4 material, calculate the trace width that can achieve 50 ohms of impedance, route the entire board according to that value, and never communicate with the factory at any point in the process. But after the factory receives the design files, they cannot source raw materials that perfectly match the parameters you preset and can only assemble a stack-up for production using prepreg and core materials they have on hand. When the final circuit boards are produced, the actual impedance jumps to 58 ohms. No one could have discovered this error in advance, and the problem is only fully exposed when the prototype units from the pilot run fail to reach the designed operating speed. By the time you make changes at that point, it is already too late.
If any circuit on your board requires impedance control, you must communicate with the factory before you start routing and never wait until the design is complete. You must take the initiative to ask the factory for their proposed stack-up plan, which must list the specific name of the material used for each layer, its corresponding dielectric constant, and the matched copper thickness—these are the foundations for you to calculate accurate impedance, and you cannot do without any one of them.
Afterwards, you must write your requirements clearly in the production notes sent to the factory, leaving no room for ambiguity: which layers require impedance control, whether the signals routed on these layers are single-ended or differential, what the target impedance must be accurate to, and what the acceptable tolerance range is (the industry standard is ±10%). In addition to this, you must agree that the factory can adjust the trace width at any time to hit the target impedance.
A reliable factory will help you simulate the actual parameters of this stack-up, then send back the corrected, precise trace width, and this entire back-and-forth communication only takes one day. But if you only discover the incorrect impedance after the circuit boards are assembled, the entire project will be delayed by a full six weeks, and the missed market window can never be recovered.
3. Solder Mask and Silkscreen Conflicts
Design conflicts between the solder mask layer and the silkscreen layer may seem like trivial cosmetic issues, but they actually carry serious functional risks, far beyond just misprinted text or chipped paint.
The most common problem is solder mask dams that are too narrow: the pads of two fine-pitch components are placed very close together, and the layer of solder mask between them is so narrow that the factory's process cannot stably print it on the board, and it will peel off entirely during production. As a result, copper is directly exposed between the pins of a QFN package chip. During reflow soldering, molten solder easily flows along the exposed copper to adjacent pins, creating a major risk of solder bridging between pins, and the entire chip is scrapped.
Most factories require that the solder mask bridge width between different pads must be at least 0.1mm; many factories that encounter dams narrower than this standard cannot produce them, so they will directly remove the dam and only notify you casually afterwards, giving you no chance to revise the design.
Another common low-level mistake is printing silkscreen directly on component pads and vias. The factory cannot allow silkscreen to block the copper foil that needs to be soldered, so they will forcibly cut off the silkscreen that covers the pads. In the end, most of the component designators left on the board are missing, and when debugging and reworking the circuit board, no one can guess which component the half-missing designator corresponds to, and repairing the board becomes a matter of guesswork.
You can avoid the vast majority of these problems by checking each item on this simple list one by one:
Add a solder mask expansion of approximately 0.05mm to each side of standard component pads, to leave sufficient margin for factory production.
The line width of silkscreen must not be narrower than 0.15mm, and the height of all silkscreen text must be at least 0.8mm, to avoid blurry prints caused by lines that are too thin or text that is too small.
Before exporting the final design files, clear all silkscreen from all exposed copper areas, and never print text in places it does not belong.
After placing all components on the board, verify that every component designator is fully visible; if a designator is blocked by a large electrolytic capacitor, it is useless to anyone working with the hardware, and printing it is a waste.
When placing pads for BGA package chips, clearly and uniformly choose either solder mask defined (SMD) or non-solder mask defined (NSMD) pads. Do not mix the two types of pads under the same chip just because you sourced two library files from different channels—this is a documented cause of assembly failures, and many people have stumbled on this issue.
4. Ignoring Assembly Footprint and Placement Rules
Some pad layouts that pass checks in layout software are completely unusable when they actually reach the factory's assembly line. The pad arrangement you copied directly from a component's datasheet is not the same as a footprint specifically designed for mass production. A datasheet only covers the parameters of the component itself; only IPC-7351 specifies the design rules that must be followed to secure a component firmly in place. Ignoring this core distinction will lead to a host of production problems that could have been completely avoided, each of which can slow down your project's progress.
The most common pitfall is tombstoning, which is also one of the most frequent assembly defects for 0402 and smaller surface-mount components. The cause of this issue is simple to explain: the thermal capacity at the two ends of a small passive component is uneven—usually one pad is directly connected to a large, solid copper area with no heat mitigation, and during reflow soldering, that pad's temperature rises much faster than the other end. The solder melts and solidifies first, pulling the entire component upright, resembling a tombstone, and the entire production line has to stop to adjust for this defective unit.
Violations of component placement restricted-area rules also deliberately slow down production: two components are placed with only 0.2mm of spacing between them, which works smoothly when you draw and route the design on your computer, but in a real factory, the pick-and-place machine's nozzle needs sufficient physical space to pick up and place components, and this small gap is completely insufficient.
When the assembly factory's quality control team catches this problem, they have to pause your order, send a dedicated engineering inquiry to raise the issue, and wait for you to confirm and complete corrections before they can resume production scheduling, wasting several days for no reason.
More basic mistakes include missing alignment markers, which make it impossible for assembly machines to register the board. If your board has neither global fiducials nor local fiducials added for fine-pitch components with small pin spacing, the pick-and-place machine has no reference points to align to and cannot start work at all.
Other issues include silkscreen polarity markers and first-pin indicators that are too blurry to confirm the direction at a glance, so operating workers have to guess. Sooner or later, someone will guess wrong and install the component backwards, and the rework required to desolder and reinstall it adds extra time costs.
To completely avoid these risks, you must first standardise your footprint library. If the pad rules you downloaded from three different vendors conflict with each other, each with its own standard, the final circuit boards produced from this mix will most likely only be able to be soldered by hand by workers and cannot be assembled in batches by machines, completely eliminating mass production efficiency.
5. Leaving Panelisation Until the Last Minute
Panelisation must be treated as a core layout requirement and never left to be added at the last minute. The vast majority of design teams finalise the outline of a single circuit board early on and only suddenly remember the need for panelisation one week before they are set to send the design for production. This order is completely backwards—panelisation has tangible hard constraints that directly affect all the designs in your core layout, and it must be considered in advance.
A factory's assembly line needs rails to firmly secure the circuit boards; generally, you must reserve a 5mm dedicated edge strip on two sides of the board and pre-drill process holes in the edge strips and place fiducials for positioning.
If you do not reserve these positions in advance, the factory can only add the edge strips outside your originally planned board outline. As a result, the overall dimensions of the entire panel change, and in some cases the panel may exceed the factory's standard processing size, unnecessarily increasing production costs.
Another common method is V-scoring, which carves a continuous groove between several small boards, so they can be broken apart by hand after the entire panel is assembled. The stress from this breaking action propagates a short distance into the board. Therefore, standard components must be placed at least 1mm away from the scoring line, and ceramic capacitors must be placed even further away; otherwise, they are easily cracked by the stress.
This type of hidden crack often only causes problems after the product is sold to a user and has been in use for a period of time, and the cost of a recall and repair at that point is extremely high.
If you use tabs and tab holes (also called "mouse bites") for panelisation, small protrusions will be left on the edge of each small board after they are broken apart. If that board edge is meant to plug into a connector or fit into a pre-designed enclosure, you will encounter a structural issue no one considered during the design phase: it simply will not fit, and the entire panel has to be scrapped.
For this reason, before you finalise the outline of a single board, you must first confirm the panelisation arrangement with the assembly factory. Spending five minutes to discuss these requirements will save you the major trouble of redrawing your entire layout, and it is well worth the effort.
Two Simple Habits That Prevent Most DFM Problems
In fact, as long as you develop two simple habits, you can catch the vast majority of problems in advance before sending your design for production, and you will never need to wait for the factory to raise them.
The first habit: after exporting the full set of production files, you must open them with independent viewing software, not the viewing tool built into the CAD software you used to draw the design. By looking directly at the actual production files you exported, rather than staying in the software's design draft, you can spot low-level mistakes like missing layers, incorrect drill file formats, and misaligned apertures in just a few minutes.
The second habit: send a preliminary package of files to your partner factory before your design is fully finalised. Most PCB factories will perform a free DFM check for you and raise all the issues they would have only brought up after you submitted the final design, in advance. At that point, making revisions is low-cost and fast, and all adjustments can still be made in time.
For example, a PCB manufacturer such asRUSH PCB can provide manufacturing and engineering support to help identify potential manufacturability problems before production. The earlier these issues are found, the less expensive they are to correct.
In addition, stop using the outdated method of packaging and compressing Gerber files, drill files, BOMs, and instruction documents to submit your files. Modern formats like ODB++ and IPC-2581 can store netlists, stack-ups, and all component data in a single file. You will never again have to worry about which version is the latest among multiple scattered files, and you can completely avoid these unnecessary troubles.
Final Thoughts
None of the steps you need to pay attention to require specialised, advanced engineering skills; they are all small tasks that ordinary people can complete with a little care.
All these recurring common mistakes stem from the same core problem: you have left ambiguous loopholes in your design files. As long as there is any unresolved, unconfirmed issue in your files, the PCB factory's staff have to stop their work and specifically ask you for an answer, and every stoppage leads to a delay of more than half a day.
Fix all these small loopholes, and the vast majority of production delays will disappear entirely, allowing your project to advance smoothly as planned.
If you want another source of PCB manufacturing and assembly information when reviewing production requirements,PCB Trace also provides PCB manufacturing, prototyping and assembly services.
The goal is simple: identify DFM problems before the factory does. A few minutes spent checking your design can save days—or even weeks—of unnecessary production delays.
